Heretofore, as a technique in this field, a technique disclosed in Patent Document 1 indicated below has been known, for example. According to the technique, slits, lattices, or dimples forming multiple grooves are formed on an end face of a cooler so that a semiconductor is brazed to that end face. This configuration prevents generation of voids in brazed portions between the cooler and the semiconductor and also disperses stress applied to a brazing material, thereby preventing the occurrence of exfoliation and cracks in the brazed portions.
However, since the “slit” may impede flow of the brazing material, a brazing start point is required on every slit surface, and thereby not-bonded portions (voids) could be generated. Further, the “lattice” may also impede flow of the brazing material, requiring a brazing start point on every lattice surface, and thereby not-bonded portions (voids) could be generated. Furthermore, since the “dimple” is to be surface-brazed, high degree of flatness of a component is required, and that could cause cost increase.